STC5230 Datasheet, PDF (38/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Default value: 63
STC5230
Synchronous Clock for SETS
Data Sheet
0x5a, bits 5 ~ 0
0
1 ~ 62
63
CLK4 2kHz output
Disabled
Pulse width 1 to 62 cycles of 155.52MHz
50% duty cycle
CLK5_Sel, 0x5b (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
0x5b
Selects or disables the CLK5 output.
Not used
Default value: 2
0x5b, bits 1 ~ 0
0
1
2
3
CLK5 output
Disabled
44.736MHz (DS3)
34.368MHz (E3)
Reserved
Bit1
Bit0
CLK5 Select
CLK6_Sel, 0x5c (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5c
Not used
Selects or disables the CLK6 output.
CLK6 Select
Default value: 1
0x5c, bits 3 ~ 0
0
1
2
3
4
5
6, 7, 8
9
10
11
12
13
14, 15
CLK6 output
Disabled
2.048MHz
4.096MHz
8.192MHz
16.384MHz
32.768MHz
Reserved
1.544MHz
3.088MHz
6.176MHz
12.352MHz
24.704MHz
Reserved
CLK7_Sel, 0x5d (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5d
Not used
CLK7 Select
Preliminary
Data Sheet #: TM102 Page 38 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007