STC5230 Datasheet, PDF (10/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

Addr
0x41
0x45
0x49
0x4d
Reg Name
T4_Long_Term_Accu_History
T4_Short_Term_Accu_History
T4_User_Accu_History
T4_History_Ramp
0x4e
0x54
0x55
T4_Priority_Table
T4_PLL_Status
T4_Accu_Flush
0x56
0x57
0x58
0x59
0x5a
0x5b
0x5c
0x5d
0x5e
0x60
0x62
0x65
CLK0_Sel
CLK1_Sel
CLK2_Sel
CLK3_Sel
CLK4_Sel
CLK5_Sel
CLK6_Sel
CLK7_Sel
Intr_Event
Intr_Enable
T0_MS_PHE
CLK8_Sel
STC5230
Synchronous Clock for SETS
Data Sheet
Table 4: Register Map
Bits
31-0
31-0
31-0
6-0
47-0
7-0
0-0
1-0
2-0
2-0
5-0
5-0
1-0
3-0
1-0
9-0
9-0
19-0
1-0
Type
R
R
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
Long term Accumulated History for T4 relative to MCLK
Short term Accumulated History for T4 relative to MCLK
User Holdover data for T4 relative to MCLK
Bits 6-4, Long term history accumulation bandwidth: 9.7, 4.9, 2.4,
1.2, 0.61, 0.03 mHz
Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62,
0.31 Hz
Bits 1-0, Ramp control: none, 1, 1.5, 2 ppm/s
REF1-12 selection priority for automatic mode, 4 bits/reference
OOP, LOL, LOS, Sync, HHR, AHR, SAP
0: Flush/reset the long-term history, 1: Flush/reset both the long-
term and the device holdover history
155.52/125 MHz clock select or disable for CLK0
19.44/38.88/51.84/77.76/25/50/125 MHz or disable select for CLK1
19.44/38.88/51.84/77.76/25/50/125 MHz or disable select for CLK2
8kHz output 50% duty cycle or pulse width selection for CLK3
2kHz output 50% duty cycle or pulse width selection for CLK4
DS3/E3 select for CLK5
DS1 x n / E1 x n selector for CLK6
DS1/E1 selector for CLK7
Interrupt event
Interrupt enable
Round-trip phase delay of T0’s cross-couple data links
155.52/125 MHz clock select or disable for CLK8
Extra Registers if LM is configured as BUS_LOAD_MODE
0x70 Bus_Loader_Status
2-0
R
0x71 Bus_Loader_Data
7-0
W
0x72 Bus_Loader_Counter
13-0
R
Status of the bus loader of the configuration data
Data port of the bus loader of the configuration data
Data counter of the bus loader of the configuration data
Extra Registers if LM is configured as EEP_LOAD_MODE
0x70 EEP_Loader_Checksum
0-0
R
0x71 EEP_Controller_Mode
7, 0
R/W
0x72 EEP_Controller_Cmd
1-0
W
0x73 EEP_Controller_Page
7-0
W
0x74 EEP_Controller_Data
7-0
R/W
Checksum status of the EEPROM loader of the configuration data
Mode of the EEPROM controller
Command to the EEPROM controller
Page number to the EEPROM controller
Data port of the EEPROM controller
Preliminary
Data Sheet #: TM102 Page 10 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007