STC5230 Datasheet, PDF (19/48 Pages) Connor-Winfield Corporation – Synchronous Clock for SETS

STC5230
Synchronous Clock for SETS
Data Sheet
T0_XSYNC_IN pins is continously measured. User
can obtain the phase delay by reading T0_MS_PHE
register (0x62-0x64). Advanced users can use this
information for their own further fault detection.
The first time a timing generator becomes a slave,
such as immediately after power-up, its output clock
phase starts out arbitrary, and will quickly phase-align
to the master unit. The phase error will be eliminated
(or converged to the programmed phase offset). The
whole pull-in-and-lock process will complete in about
16 seconds. There is no frequency ramp protection in
slave mode.
Activity of the signals on the T(0/4)_XSYNC_IN pins
is available in the Refs_Activity register (0x18/19).
(The leaky bucket algorithms are not applied to these
signals.)
Note the phase alignment of all clock outputs from the
T0 timing generator with the 2kHz output.
Once a pair of timing generators has been operating
in aligned master/slave mode, and a master/slave
switch occurs, the timing generator that becomes
master will maintain its output clock phase and fre-
quency while a phase rebuild is performed on its
selected reference input. Therefore, as master mode
operation commences, there will be no phase or fre-
quency hits on the clock output. Assuming the phase
offset is programmed for the actual delay of this
cross-couple path, there will again be no phase hits
on the output clock of the timing generator that has
transitioned from master to slave.
Master T4
Clock
T1/E1
Synthesizer
STC5230
Slave T4
Clock
T1/E1
Synthesizer
STC5230
Programmable compensation
from 0 to 409.5 ns
Functional Specification
Event Interrupts
STC5230 could provide notice interrupts to the host
processor via pin EVENT_INTR (pin 32). A hand of
certain events can be programmed to trig interrupts.
User can turn on and off of each event individually by
writing to register Intr_Enable (0x60-0x61). The
associated events which trigged interrupts will be
latched. After detected the assert of interrupt pin,
application can read the list of latched events from
register Intr_Event (0x5e-0x5f). User can clear the
events by writing a ‘1’ to the bit position of each
related event. The pin EVENT_INTR returns to nor-
mal when no more event latched.
There are 10 different events can be programmed to
trig the interrupts. The list covers the some status
change of each timing generator and the change of
qualification status of input references. The status
change of the timing generator includes the change of
the active reference in automatic reference selection
mode, the change of the DPLL status, and the
change of the cross reference activity. Each event
could be enabled and disabled individually.
Field Upgrade Feature
The initialization of registers and DPLL detailed
behavior is defined by the hardware and firmware
configuration data. Following any device reset, either
via power-up or operation of the reset pin, the device
needs to be loaded with the configuration data. This
data may be loaded from the internal ROM (pro-
grammed with factory default data), an optional exter-
nal EEPROM, or from the bus interface.
Externally supplied data provides the option to accept
future field upgrades. For external data loading, the
manufacturer may provide the configuration data per
a specific customer agreement.
Load mode configuration pins
The load mode configuration pins LM0 and LM1
determine the configuration data pump method, as
shown in table 5:
Figure 9: T4 CLK7 Master/Slave Skew Control
Preliminary
Data Sheet #: TM102 Page 19 of 48
Rev: P01
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: August 22, 2007