CN8223 Datasheet, PDF (96/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

3.0 Registers
3.3 Configuration Control Registers
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
Bit
Field
Size
Name
Description
4
1
Check Input Parity Enables parity checking at the FIFO port inputs. This bit must be enabled for the
input parity error status bits or interrupts to be active.
3
1
Disable Write
Inhibits the receive port FIFO write strobes when a cell is determined to be invalid
Strobes on Invalid for use with generic FIFOs.
Cells
2
1
Enable DS1 PRS
Causes the physical layer data content to be replaced by a quasi-random signal
Generator
stream. This stream is used for certain transmission tests in DS1 systems.
1
1
HEC Coverage
Determines the calculation range for the HEC. If this bit is low, the HEC is calculated
over header octets 1–4 for ATM cells. If this bit is high, the HEC is calculated over
header octets 2–4 for SMDS/802.6 cells.
0
1
Enable HEC Coset
Enables the x⁶ + x⁴ + x² + 1 polynomial to be XOR’ed with the calculated HEC prior
to transmission and prior to error detection/correction if HEC is internally
generated. For TAXI mode, enable HEC Coset must be active.
0x29—CONFIG_4 (Configuration Control Register 4)
The CONFIG_ 4 register is located at address 0x29 and controls miscellaneous functions.
Bit
Field
Size
Name
Description
15-12 4
11-8 4
7-4
4
3
1
2
1
1
1
0
1
Disable CRC
Check-Ports 3–0
Disable Length
Check-Ports 3–0
Disable Port
Reception-Ports
3–0
Enable TAXI
Interface
Delete Idle Cells
Enable External
Section Trace
STM-1/STS-3c
Pointer
Disables the payload CRC check on a per-port basis. This disable controls only the
output of cells to the FIFO interface and does not control the counting of payload
CRC errors. (Counts are performed collectively, not per port.)
Disables the payload length check on a per-port basis. This disable controls only the
output of cells to the FIFO interface and does not control the counting of payload
length errors. (Counts are performed collectively, not per port.)
Disables the output of any received cells on a per-port basis. This disable control is
internally synchronized to cell boundaries so that no partial cells are output on a
port.
Enables an interface specific to 100 Mbps 4B/5B data transceivers on the parallel
interface port. This interface is detailed in Section 2.5.1.
Allows the screening of cells matching the receive idle header and mask criteria
from appearing on the outputs of any of the receive ports. When this bit is low, idle
cells are not automatically screened from port output. When this bit is high, idle
cells are screened from output on the receive FIFO port.
Allows the section trace octet (C1) to be inserted externally. When this bit is low, the
C1 octet is generated internally. When this bit is high, the C1 octet is inserted from
the TXOVH input bus.
Enables the SS bits to be generated in the AU-4 pointer for STM-1 compatibility.
When this bit is low, an STS-3c H1/H2 pointer is generated by the transmitter (no SS
bits present) and the C2 octet⁽¹⁾ has the value 0x13. When this bit is high, an STM-1
AU-4 pointer is generated with the SS bits set to 10.
NOTE(S):
(1) _{The C2 octet is the STS Path Signal Label. It is allocated to indicate the content of the STS SPE, including the status of the}
mapped payloads.
3-10
Conexant
100046C