CN8223 Datasheet, PDF (100/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

3.0 Registers
3.4 Transmit Control Registers
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
3.4 Transmit Control Registers
0x03—TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register)
The TXFEAC_ERRPAT register is located at address 0x03. The eight MSBs control the FEAC channel used for
DS3. Programming of the FEAC channel is discussed in Section 2.8.
The eight LSBs of this register insert BIP-8 errors in the transmitted PLCP, G.832, or SONET overhead or
HEC errors in the cell header for end-to-end testing. The error pattern is XOR’ed with the selected field that is
to be errored.
Bit
15–10
9
8
7–0
Field
Size
6
1
1
8
Name
Transmit FEAC Data
Enable FEAC
Transmission
Enable Receive
FEAC Interrupt
Error Insertion
Pattern
Description
Six bits of serial data.
Enables FEAC transmission; message is transmitted 10 times. Interrupt on DL_INT
when done.
Turns on the interrupt for the FEAC receive.
BIP-8 errors for PLCP, G.832, or SONET.
3-14
Conexant
100046C