CN8223 Datasheet, PDF (93/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
3.0 Registers
3.3 Configuration Control Registers
0x01—CONFIG_2 (Configuration Control Register 2)
The CONFIG_2 register is located at address 0x01 and controls transmit formatting and alarm generation.
Table 3-4 defines Alarm Controls for the Line Framing/PHY Formats. Table 3-5 defines the control bits for
STS-1/STS-3c/STM-1. Table 3-6 defines the overhead bits for Line Framing/PHY Formats.
Bit
Field
Size
Name
15
1
Enable External
Overhead
14
1
All-Zeros FEBE
13
1
All-1s FEBE
12–10 3
BIP Error Insert
9–4
6
Transmit Alarm
Control
3–0
4
Overhead Control
Description
Enables all overhead octets to be inserted externally in STS-1/STS-3c/STM-1 and
G.832 E3/E4 modes. If this bit is not set, internal generation of overhead octets is
enabled as described in Section 2.3.
Inserts an all-0s value in the FEBE field. The all-0s value provides an indication at
the far end that no BIP-8 errors are being detected. BIP-8 status and error counts
are not affected. This control bit is active in all modes whether the FEBE field is
single- or multi-bit.
Inserts an all-1s value in the FEBE field of the transmit frame. The all-1s value
notifies the far end that the FEBE function is inhibited. BIP-8 status and error counts
are not affected. This control bit is active in all modes whether the FEBE field is
single- or multi-bit.
Selects the BIP field that will be errored with the TXFEAC_ERRPAT register
according to the following:
Bit 12
0
0
0
0
1
1
1
1
Bit 11
0
0
1
1
0
0
1
1
Bit 10
0
1
0
1
0
1
0
1
BIP Field to be Errored
No errors inserted
B1 field (all modes)
B2 field, bits 23:16 (STS-3c/STM-1 mode only)
B2 field, bits 15:8 (STS-3c/STM-1 mode only)
B2 field, bits 7:0 (STS-1/STS-3c/STM-1 modes)
B3 field (STS-1/STS-3c/STM-1 modes)
No errors inserted
B2 field, all 3 octets (STS-3c/STM-1 mode)
These bits are cleared by the transmitter after the error is inserted in the overhead
field, and can be read as 0 to verify that error insertion has taken place.
Controls the generation of alarms for 57-octet PLCPs and internal framers. No
alarms are transmitted if all bits in this control field are set to 0. Setting any of these
bits to a 1 causes an alarm to be transmitted according to Table 3-4 and Table 3-5.
For example, in STS-3c mode, setting bit 4 to a 1 will cause the Line AIS alarm to be
transmitted.
Selectively disables overhead generation. Standard overhead is generated internally
if all bits in this control field are set to 0. Overhead sources for all PHY modes are
given in Table 2-8. When a particular overhead field is set to be disabled, it will be
filled with 0s. Overhead generation is disabled dependent on mode, according to the
data in Table 3-6.
100046C
Conexant
3-7