CN8223 Datasheet, PDF (63/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0 Functional Description
2.6 ATM Cell Processing
2.6.2 Cell Validation for Receive
Cell validation refers to the checking of cells coming in from the PHY block for
proper format. Modes that deliver 48-, 52- or 53-octet cells, or 57-octet PLCP
slots to the FIFO output ports are provided by the CN8223.
Four modes are available for cell output:
• A test mode writes the entire 57-octet PLCP slot to the FIFO interface.
• A 53-octet mode writes the 53-octet ATM cell to the FIFO interface.
• A 52-octet mode writes the ATM cell without the HEC octet to the FIFO
interface.
• A final mode delivers 48-octet cell payloads to the FIFO interface.
When the UTOPIA interface mode is used, only 53-octet output is available.
The protocol verification provided includes HEC validation with ATM or
SMDS/802.6 coverage, cell header filter/screen against four maskable 32-bit
programmable values, validation of payload length per segment type, and correct
payload CRC value. Status reporting on validation steps is via error counters and
status register indications. Status bits can be programmed to generate interrupts to
the microprocessor. Each validation step can be individually disabled. Cells are
routed to one of four output ports if a match to that port’s programmable header
value is made.
Each cell is output to the ATM interface after a 6- or 10-octet buffer to allow
for header processing. A “cell-valid” output pin is provided to indicate that none
of the enabled error checks detected an error. The UTOPIA internal FIFO or
external circuitry is notified to discard the cell when the valid indication goes
inactive. Idle cells are automatically deleted from the ATM layer output. Parity
and control/delineation signals are provided with each octet at the port interface.
The microprocessor receives status and error counts as cell validation proceeds.
All event and error counters can be programmed to cause an interrupt on
overflow. Reading the interrupt source register allows the microprocessor to
identify overflows and update internal counts. All counters can be read by the
microprocessor and are cleared when read.
100046C
Conexant
2-29