CN8223 Datasheet, PDF (78/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description
2.8 FEAC Channel and HDLC Data Link Programming
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.8 FEAC Channel and HDLC Data Link
Programming
This section discusses the use and programming requirements for the FEAC
channel and HDLC data link. The FEAC channel is used in DS3 mode; the
HDLC data link is used by DS3, E3, and STS-1/3 framers.
2.8.1 FEAC Channel Transmitter
The FEAC Channel transmitter is under control of the PHY Type [bits 2–0],
External Framer [bit 5] of CONFIG_1 [0x00], Transmit Alarm Control [bits 9–4
of CONFIG_2 [0x01], Enable FEAC Transmission [bit 9], and Transmit FEAC
Data [bits 15–10] of TXFEAC_ERRPAT [0x03]. An interrupt for use with FEAC
channel operations is available on the DL_INT output pin, and status bits for
determining the interrupt source are located in the RXFEAC_VER register
[0x3C].
The PHY type must be set to internal DS3 for FEAC channel transmission to
take place. In DS3 mode, the last C bit in subframe 1 of the M-frame is used for
transmission. Setting the Transmit Alarm Control [bits 9–4] for transmission of
AIS disables transmission of the FEAC channel. Transmission of yellow alarm or
idle code has no effect on FEAC channel transmission.
The TXFEAC_ERRPAT register controls the byte to be transmitted on the
FEAC channel. All messages for transmission on the FEAC channel must be in
the form “0xxxmmm011111111”. The right-most bit of this sequence is the first
bit transmitted on the channel. To initiate transmission of a message byte in the
FEAC channel, write the desired byte in the form “mmmxxx” into bits 15–10 of
the TXFEAC_ERRPAT register. A 1 must be written to Enable FEAC
Transmission [bit 9]. Transmission of the flag (11111111) and the 0s on either
side of the “xxxmmm” pattern is automatic. Ten repetitions of the message are
sent before an interrupt is issued on the DL_INT pin. The interrupt also appears
in the RXFEAC_VER register to request a new byte from the processor. To clear
the interrupt, you must write the TXFEAC_ERRPAT register. Each time a new
byte is written, 10 transmissions of that byte (and flag) will automatically occur.
Interrupts from the transmit FEAC channel will occur at a rate of approximately
one interrupt per 17 ms.
If you write a 0 to Enable FEAC Transmission [bit 9], then continuous
transmission of idle flags is enabled and no interrupts are issued until a byte of the
proper format is written to the TXFEAC_ERRPAT register. Interrupts from the
FEAC channel transmitter appear on Transmit FEAC Interrupt [bit 8] in the
RXFEAC_VER register [0x3C].
2-44
Conexant
100046C