CN8223 Datasheet, PDF (57/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0 Functional Description
2.5 Parallel Line Interface
Timing information for TAXI mode is found in Section 4.3.5. Pin connections
for the TAXI chipset and the CN8223 are listed in Table 2-14.
Table 2-14. Pin Connections between TAXI Chipset and CN8223
Signal Name from TAXI Chipset
Connect to CN8223 Pin
Receive Clock (CLK)
Receive Data (DO 7-0)
Receive Command (CO 1)
Receive Command Strobe (CSTRB)
Receive Violation (VLTN)
Transmit Clock (CLK)
Transmit Data (DI 7-0)
Transmit Command (CI 1)
Transmit Command (CI 0,2,3)
Transmit Strobe (STRB)
RXCKI
RXIN[7:0]
TXIN
RCV_HLD
RXIN[8]
TXCKI
TXOUT[7:0]
TXOUT[8]
GND
TCLKO
2.5.2 Transmit Parallel Interface
Interface connections for the Transmit Parallel Interface mode are listed in
Table 2-15. TXOD and TXDELO are mapped to TXIN and TXOUT[8],
respectively. Figure 2-14 illustrates the transmit timing for the parallel interface.
TXCKI has a frequency of up to 20 MHz. In parallel mode, the synchronization
signal TXOD marks the octet clocks where the CN8223 does not provide a new
data octet on the TXDAT output. This could be used for marking all of the
overhead (non-ATM payload) octets in a data stream.
Alternatively, TXOD can be held low and a gapped octet clock provided from
the external circuitry to the CN8223 on TXCKI. TXDAT is the output signal; it
transitions in response to the rising edge of TXCKI, and can be sampled on the
following falling edge externally. TXDELO also transitions in response to the
rising edge and marks the first octet of each 53-octet cell.
Table 2-15. Transmit Parallel Interface Mode Connections
Signal Name
Connect to CN8223 Pin
Transmit Clock Input (TXCKI)
Transmit Octet Disable (TXOD)
Transmit Data Output (TXDAT)
Transmit Cell Delineation (TXDELO)
TXCKI
TXIN
TXOUT[7:0]
TXOUT[8]
100046C
Conexant
2-23