CN8223 Datasheet, PDF (36/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description
2.1 Microprocessor Interface
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.1 Microprocessor Interface
All control and status functions are provided via a direct microprocessor
interface. Address maps for the microprocessor are given in Chapter 3.0. There
are two types of address spaces:
• Read and write control registers
• Read-only status registers and counters
Write operations are fully decoded. Write operations to undefined addresses have
no effect. Read operations from undefined addresses have undefined results.
The microprocessor interface to the CN8223 consists of 31 pins (detailed in
Table 1-2). The CN8223 connects to the microprocessor as if it were clocked
RAM memory. For timing diagram details, see Section 4.3.1.
2.1.1 8/16-Bit Interface
The CN8223 supports an 8-bit or 16-bit microprocessor interface. To select the
8-bit data bus, connect the SEL8BIT pin to VCC. This configures all control and
status registers in the part for byte-wide operation. Byte addressing is
accomplished by using the D15 pin as the byte high/low select. When D15 is low,
the low byte of the addressed register is read or written, and the high byte is
unaffected. When D15 is high, the high byte of the addressed register is read or
written, and the low byte is unaffected. When reading register locations, the high
byte of the addressed location is internally latched so that it can be read in the
next operation. Therefore, the low byte of a word address should be read first,
then the high byte, to prevent loss of data. When SEL8BIT is low, the interface is
configured with a 16-bit bus.
2.1.2 Interrupts
The CN8223 is designed for an interrupt-driven environment. After initialization,
status events, error events, and counter overflows generate interrupts that run
appropriate interrupt service routines.
Two active-low interrupt pins are provided for the microprocessor interface.
STAT_INT provides interrupts for all status and error conditions. DL_INT
provides interrupts for the Far End Alarm Control (FEAC) channel contained in
the internal DS3 framer and for the internal High-Level Data Link Control
(HDLC) formatter used for various data links. Both interrupt pins are configured
as open drain to facilitate external wire-OR connections.
Each interrupt source has a bit in an interrupt enable register and in an
interrupt status register. This allows the microprocessor to control which
conditions cause interrupts and to determine the source of the interrupt. The
status registers are described in Chapter 3.0.
NOTE: Receiver interrupts will not function if the receive clock is not active. For
example, if losing the signal to the line interface causes the receive clock
recovery circuit to be disabled, the CN8223 will not respond to an LOS
interrupt.
2-2
Conexant
100046C