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CN8223 Datasheet, PDF (107/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface | |||
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CN8223
ATM Transmitter/Receiver with UTOPIA Interface
3.0 Registers
3.5 Receive Control Registers
0x15â0x1CâHDR_VALx_12, HDR_VALx_34 (Receive Header Value Register)
The Receive Header Value registers for port x (where x can be 0 to 3) are located at addresses 0x15â0x1C. The
header values direct ATM cells to each port. If an incoming ATM cell header matches the value in the header
register, the cell is directed to that port. Receive Header Mask registers further qualify ATM cell reception.
Table 3-9 defines the HDR_VALx register addresses.
Table 3-9. HDR_VALx Register Addresses
Address
Register Name
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
HDR_VAL0_12
HDR_VAL0_34
HDR_VAL1_12
HDR_VAL1_34
HDR_VAL2_12
HDR_VAL2_34
HDR_VAL3_12
HDR_VAL3_34
Description
Receive Port 0 ATM Header ValueâOctets 1, 2
Receive Port 0 ATM Header ValueâOctets 3, 4
Receive Port 1 ATM Header ValueâOctets 1, 2
Receive Port 1 ATM Header ValueâOctets 3, 4
Receive Port 2 ATM Header ValueâOctets 1, 2
Receive Port 2 ATM Header ValueâOctets 3, 4
Receive Port 3 ATM Header ValueâOctets 1, 2
Receive Port 3 ATM Header ValueâOctets 3, 4
HDR_VAL0_12, HDR_VAL1_12, HDR_VAL2_12, HDR_VAL3_12
Bit
Field
Size
Name
Description
15â8
7â0
8 Header ValueâOctet 1 Receive Port X ATM Header Match ValueâOctet 1
8 Header ValueâOctet 2 Receive Port X ATM Header Match ValueâOctet 2
HDR_VAL0_34, HDR_VAL1_34, HDR_VAL2_34, HDR_VAL3_34
Bit
Field
Size
Name
Description
15â8 8
7â0
8
Header ValueâOctet 3
Header ValueâOctet 4
Receive Port X ATM Header Match ValueâOctet 3
Receive Port X ATM Header Match ValueâOctet 4
100046C
Conexant
3-21
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