CN8223 Datasheet, PDF (138/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

4.0 Electrical and Mechanical Specifications
4.3 Timing
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
4.3 Timing
This section includes timing diagrams and descriptions for the CN8223.
4.3.1 Microprocessor Interface Timing
Table 4-2 and Figure 4-1 display the timing requirements and characteristics of
the microprocessor interface. All times are in nanoseconds.
Table 4-2. Microprocessor Interface Timing
Name
Description
tprclk
tprh
tprl
taspr
tapr
tcspr
tcsph
twpr
tpras
tdpr
tprd
todd
todv
todi
todz
tpdd
tpdv
tpdi
tpdz
Processor Clock Period
Processor Clock Pulse Width High
Processor Clock Pulse Width Low
Address Strobe Setup to Processor Clock Rising Edge
Address Setup to Processor Clock Rising Edge
Chip Select Setup to Processor Clock Rising Edge
Chip Select to Processor Clock Rising Edge Hold Time
Write/Read Control Setup to Processor Clock Rising Edge
Address Strobe Hold after Processor Clock Rising Edge
Data Setup to Processor Clock Rising Edge (write cycle)
Data Hold after Processor Clock Rising Edge (write cycle)
Output Enable Low to Data Bus Driven (read cycle)
Output Enable Low to Data Bus Valid (read cycle)
Output Enable High to Data Bus Invalid (read cycle)
Output Enable High to Data Bus High-Z (read cycle)
PRCLK High to Data Bus Driven (read cycle, OE~ low)
PRCLK High to Data Bus Valid (read cycle, OE~ low)
PRCLK high to Data Bus Invalid (read cycle, OE~ low)
PRCLK High to Data Bus High-Z (read cycle, OE~ low)
Min
30
10
10
4
1
4
8
1
tprh + 2 ns
1.0
3.0
1.5
1.6
1.3
1.4
3.5
3.6
3.2
3.2
Max
2X Cell Rate
—
—
—
—
—
—
—
tprl – 4 ns
—
—
6.0
6.0
4.9
5.1
11.0
11.0
10.0
10.0
4-4
Conexant
100046C