CN8223 Datasheet, PDF (77/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0 Functional Description
2.7 FIFO Port/UTOPIA Interface
If Delete Idle Cells [bit 2] of CONFIG_4 [0x29] is set, then received cells
matching the idle header and mask criteria are automatically screened from
appearing on the output of all ports.
This idle cell screening is in addition to any reject values that are programmed
for the individual ports. Only addressed ports have active strobes.
2.7.5 UTOPIA Interface
The CN8223 incorporates an interface that is compliant with both the ATM
Forum UTOPIA Level 1 (Version 2.01) Specification and the Saturn Compliant
Interface for ATM PHY Devices Specification.
When the UTOPIA interface is enabled, the CN8223 becomes a single port
device with all input and output of cell data taking place on Port 0.
Configurations for ports 1, 2, and 3 (such as header values and masks or rate
controls) are ignored when in UTOPIA mode. The header values, masks, rate
controls, and other per-port configuration control bits for Port 0 govern the
operation of the UTOPIA port cell stream.
The UTOPIA interface contains transmit and receive buffer FIFOs with a
depth of four cells and is programmable for reduced latency requirements per
ATM Forum document 94/0317. UTOPIA interface pins are listed in Table 2-27.
The UTOPIA interface is controlled by 0x2B—UTOPIA_1 (Utopia Port
Control Register 1) and 0x2C—UTOPIA_2 (Utopia Port Control Register 2). The
timing for the UTOPIA interface is functionally compatible with the timing
shown in the Version 2.01 ATM Forum Specification. Detailed timing
information can be found in Chapter 4.0.
Table 2-27. UTOPIA Interface Pins
UTOPIA Signal
CN8223 Pin
Signal Direction Relative to
CN8223
TxData (7:0)
TxPrty 0
TxSOC
TxEnb~
TxClk
TxFull~/TxClav
RxData (7:0)
RxPrty 0
RxSOC
RxEnb~
RxClk
RxEmpty~/RxClav
—
—
RcvFifoOverflow
FDAT_IN[7:0]
FDAT_IN[8]
FCTRL_IN[0]
FCTRL_IN[1]
FCTRL_IN[2]
FCTRL_OUT[2]
FDAT_OUT[7:0]
FDAT_OUT[8]
FCTRL_OUT[0]
FCTRL_IN[3]
FCTRL_IN[4]
FCTRL_OUT[1]
FCTRL_IN[5:7]
FCTRL_OUT[16:4]
FCTRL_OUT[3]
In
In
In
In
In
Out
Out
Out
Out
In
In
Out
Reserved, Connect to Ground
Undefined Output
Out
100046C
Conexant
2-43