CN8223 Datasheet, PDF (12/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

1.0 Product Description
1.1 Block Diagram
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
Figure 1-1. CN8223 Detailed Block Diagram
TMRKR
TOVH_CLK TXOVH
8
DL_INT
STAT_INT
PRCLK
CS~
AS~
W/R~
OE~
A[7:1] D[15:0] SEL8BIT
8
16
TCLKO_HS±
TXOUT_HS±
TXCKI_HS±
RXCKI_HS±
RXIN_HS±
TCLKO
TXOUT
TXCKI
RXCKI
RXIN
RCV_HLD
LOCD
TXOUT[7:0] ⁹
RXIN[7:0]
9
Line
Interfaces
High
Speed
Medium
Speed
Parallel
Interface
Tx
Tx
HDLC FEAC
Tx
Overhead
Insert
Cell Counters
Performance
Monitoring
Interrupt Control
Microprocessor
Interface
DS3, E3, E4, STS-1
STS-3c, STM-1
G.832
Transmit Framer
Transmit G.832
and PLCP
Framer
Tx Cell
Generation,
Tx Rate
and Priority
4-Port
FIFO
Data
Interface
Port 0 Ctrl
Port 1 Ctrl
Port 2 Ctrl
DS3, E3, E4, STS-1
STS-3c, STM-1
G.832
Receive Framer
Receive G.832
and PLCP
Framer
Rx Cell
Validation
Rx VPI/VCI
Screening
Rx
Rx
HDLC FEAC
Rx
Overhead
Extract
Clock and
Control
UTOPIA
Interface
and
4-Cell
Buffers
Port 3 Ctrl
UTOPIA Ctrl
9
9
CN8223
FCTRL_OUT[16:0]
FCTRL_IN[7:0]
FDAT_IN
FDAT_OUT
8
RMRKR RXOVH
ROVH_CLK
ONESECI
8KCKI
NTEST
TEST1, 3
RESET
ONESECO
Line Framer Section
Cell Processing
Section
FIFO Data Ports Section
1-2
Conexant
100046C