CN8223 Datasheet, PDF (76/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description
2.7 FIFO Port/UTOPIA Interface
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.7.4.1 Header
Screening
The HDR_MSKx_12 and HDR_MSKx_34 registers further qualify the bitwise
values in the Header Value registers. There are four sets of these registers (x = 0,
1, 2, 3), one set for each of the four receive FIFO ports. A bit set to 1 in a Header
Mask register sets the same bit position in the Header Value register to a Don’t
Care condition for accepting cell headers.
An example of Header Value and Mask register screening for cells received by
FIFO Port 0 follows:
HDR_VAL0_12 = 0000 H
HDR_VAL0_34 = F000 H
HDR_MSK0_12 = 0000 H
HDR_MSK0_34 = 0000 H
This header screening setup for FIFO Port 0 receives cells with octets 1 2 3 4
equal to 00 00 F0 00. Since the Header Mask bits for Port 0 are all 0, there is no
effect on the header value screening.
In the following example the Header Mask value allows multiple cells to be
accepted by FIFO Port 0:
HDR_VAL0_12 = 0000 H
HDR_VAL0_34 = F000 H
HDR_MSK0_12 = 0000 H
HDR_MSK0_34 = 0003 H
2.7.4.2 Output
Screening
This header screening setup for FIFO Port 0 accepts four different received
cells with octets 1 2 3 4 equal to 00 00 F0 00, 00 00 F0 01, 00 00 F0 02, or 00 00
F0 03. The 2 bits set in HDR_MSK0_12 set Don’t Care conditions for the same 2
bit positions in HDR_VAL0_12. This allows four different ATM cell headers to
be accepted by FIFO Port 0.
These control registers enable the CN8223 to be programmed to accept only
certain slot types, or all slots whether busy or not, and also to screen slots for a
particular VCI/VPI pattern. To disable header screening completely, write the
mask register to all 1s. Headers are screened after any error correction is
performed by the HEC circuitry.
The receiver circuitry contains buffer storage so that the header octets can be
examined to determine which, if any, port is to be activated for output. This
allows output of the PLCP and header octets in 57- and 53-octet modes,
respectively.
Header octets are compared to the programmed values in the HDR_VAL
registers under control of the HDR_MSK registers. If a match is made, the data
write strobe for that port is activated, and the cells are written to the port. By
using the mask bits to mark Don’t Care locations, cells with different header
values can be sent to a single port. This allows entire VCI/VPI “pages” to be sent
to the same location. Also, several ports can be programmed to receive cells with
the same header values or overlapping pages of header values resulting in a
programmable broadcast capability.
If Accept/Reject [bits 15–12] in CONFIG_3 [0x02], is set for a particular port,
then all cells with headers matching the programmed header value and mask
criteria are rejected by the port, and all other cells are accepted for output. This
feature can be used to screen certain VCI/VPI values from being output to a
particular port.
2-42
Conexant
100046C