CN8223 Datasheet, PDF (64/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description
2.6 ATM Cell Processing
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.6.2.1 HEC Alignment
2.6.2.2 CELL_VAL
Control Register
In 53-octet mode, either the internal framer or the parallel input provides octet
alignment information to the HEC alignment state machine. Each octet position is
then searched for correct HEC alignment to determine cell delineation. The HEC
alignment framing state machine is given in ITU I.432. Three states are present:
hunt, pre-sync, and sync. The hunt state is entered when seven consecutive
errored HEC patterns are found at the current alignment location. The pre-sync
state is entered when a candidate position contains the correct HEC pattern. The
sync state is entered when six consecutive, correct HEC patterns at the candidate
location are found.
The HEC state machine can be altered to include state integration by setting
the Integrate HEC Framing control bit in CONFIG_5. When this bit is set, the
state machine has two additional states: OCD Anomaly and Verification. The
OCD Anomaly state is entered when seven consecutive errored HEC patterns are
found at the current alignment location. OCD Anomaly status is indicated in bit
10 of CONFIG_5. After an integration time of X ms in the OCD Anomaly state,
the LCD defect state is entered. The LCD defect state is indicated in bit 8 of
LINE_STATUS [0x38] and on the LOCD output pin. The verification state is
entered when six consecutive, correct HEC patterns at the candidate location are
found. After x ms in the verification state, the sync state is entered. The value of x
is 4 ms for SONET/SDH modes and 2.5 ms for DS3 mode. This integration time
is counted from the 8 kHz reference input on the 8KCKI input pin. A rising edge
must be present on this input every 125 µs for proper integration in this state
machine.
Cell validation refers to the error checking of received cells prior to output to the
FIFO interface. It is controlled via the CELL_VAL register [0x14]. Per-port
output mode selects 48-, 52-, 53-, or 57-octet modes for each of the four ports.
Enable HEC Correction [bit 8] enables the HEC correction mode for single-bit
header errors. If this bit is set to zero, then no correction is performed, but error
detection is always performed. Error correction must be disabled if HEC
Coverage [bit 1] in CONFIG_3 [0x03] is set for SMDS/802.6 mode, or if Enable
HEC Coset [bit 0] in CONFIG_3 is not enabled.
Header Only Output [bit 12] in CELL_VAL enables a 5-octet output mode on
Port 3. Only the 4 header octets of cells addressed to Port 3 and the status octet in
Table 2-19 are output to the FIFO port. In 53-octet cell formats, if status output is
enabled with Header Only Output, none of the other ports should be programmed
for 53-octet output.
Enable Status Octet [bit 13] in CELL_VAL sends a status octet to FIFO Port 3.
It should only be used in 53-octet output mode. When this bit is set, the HEC octet
position in the FIFO output data is omitted, and a status word as shown in
Table 2-19 is appended to the end of the cell as octet number 53. In 53-octet cell
formats, if status output is enabled with the Enable Status Octet bit, none of the
other ports should be programmed for 53-octet output.
The status word contains indications of Port 3 header and payload errors as
well as VCI/VPI match information for the other three ports for each cell
received. The status word bits are set only if the corresponding failure occurs and
the check for that failure is enabled. The User Data Bit is derived from the PT
field in the header as shown in Table 2-20 and can be used as an AAL5 EOM
marker. These two Port 3 output options are available only if none of the ports are
set to 57-octet output mode.
2-30
Conexant
100046C