CN8223 Datasheet, PDF (140/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

4.0 Electrical and Mechanical Specifications
4.3 Timing
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
4.3.2 Line Interface Timing
Tables 4-3 through 4-6 and Figures 4-2 through 4-5 display the timing
requirements and characteristics of the line interfaces and parallel data and
overhead ports. All times are in nanoseconds. Example LIU circuits are provided
in CN8223 EVM schematics.
Table 4-3. Line Interface Timing—DS1, E1, DS3, E3 External Framers
Name
Interval
Description
ttxcki
1–7
Transmit Clock Period⁽¹⁾
ttxh
1–4
Transmit Clock Pulse Width High⁽²⁾
ttsck
3–4
Transmit Sync Setup to Transmit Clock Falling Edge
tckts
4–6
Transmit Sync Hold after Transmit Clock Falling Edge
tckd1
1–2
Transmit Clock Rising Edge to DS1/E1 Serial Data Out
tckd2
4–5
Transmit Clock Falling Edge to DS3/E3 Serial Data Out
trxcki
8–13
Receive Clock Period
trxh
8–11
Receive Clock Pulse Width High⁽²⁾
trsck
9–11
Receive Sync Setup to Receive Clock Falling Edge
tckrs
11–12
Receive Sync Hold after Receive Clock Falling Edge
trdck
10–11
Receive Data Setup to Receive Clock Falling Edge
tckdr
11–14
Receive Data Hold after Receive Clock Falling Edge
NOTE(S):
(1) _{Nominal clock periods are:}
DS1 –648 ns
E1 –488 ns
E3 –29.1 ns
DS3 –22.4 ns
(2) _{Duty cycle must be 40/60 at maximum input clock rate.}
Min
Max
22
—
8.8
—
0
—
2.4
—
2.9
12.2
2.9
10.4
22
—
8.8
15
0
—
3.4
—
2.3
—
2.6
—
4-6
Conexant
100046C