CN8223 Datasheet, PDF (81/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0 Functional Description
2.8 FEAC Channel and HDLC Data Link Programming
2.8.3.2 Aborting a
Message
2.8.3.3 Transmitter
Interrupts
The 3-bit field TxBytes[2:0] is functionally split into two parts. The most
significant bit (MSB) indicates to the transmitter circuitry which half of the buffer
to read from next. The two LSBs indicate the stop location, i.e., where the last
message byte is located. When the new controls are latched by the transmitter
circuitry, the processor is interrupted for the next set of controls. Now, the
processor has up to 4-byte intervals (byte transmission time periods) to write a
new set of controls to the control register. Because of a race condition, the ISR
that is processing the transmit interrupt must delay 1.5 byte times before writing a
new control register value. The processor can now write the next block of data to
the next half of the message buffer.
When the end of a message is reached, or in the event of a short message, there
may not be exactly 4 bytes remaining. In this case, the processor writes the
remaining data to the message buffer as usual. The processor now must write the
highest location used to the TxBytes[2:0] field in the data link control register.
Send FCS is set to 1. This causes the FCS to be sent after this last block of data.
When this set of controls is latched, the processor is interrupted. At this time a
new message can be sent, or Send Message can be set to 0 to send idle flags. If a
new message is to be sent immediately, the next half of the transmit buffer can be
written, and the data link control register configured accordingly. This results in
only one idle flag being transmitted between messages. If there is no new
message ready, the processor must write Send Message to 0. If this is not done
within 4 byte intervals, undefined data is transmitted.
To abort a message in progress, the controller writes Abort Message to 1 in the
data link control register. The transmitter finishes sending the message byte in
progress, then transmits an abort flag (11111110). After writing the abort signal
to the control register, a second write may follow the next interrupt to cause the
transmitter to go to the idle condition or to transmit another message. In the latter
case, the abort flag is followed by one idle flag, and the new message begins. If
the second write is not performed, the formatter continues to transmit abort flags
until instructed otherwise.
The transmitter generates an interrupt when it has latched the present set of
controls and is ready for a new set. There are no interrupts during the
transmission of idle flags. Therefore, to start a message from an idle condition,
the processor writes the first half of the buffer and the proper control bits. When
the circuit latches these controls internally, an interrupt is immediately issued for
the next set of control bits. The processor then has up to 4 byte intervals to
respond to the interrupt. The interrupt appears on the DL_INT pin. The
DL_CTRL_STAT register indicates the source of the interrupt but not the cause.
The controller software must know from the message context what response is
required. The interrupt is an active low level, not a pulse. The transmit interrupt is
cleared upon the writing of the DL_CTRL_STAT register. A write operation must
be performed to clear the current interrupt and prevent missing later interrupts.
If the interrupt is a mid-message interrupt, a new data link control word must
be written with TxBytes[2:0] equal to the ending location of the next message
block. The MSB of TxBytes[2:0] informs the transmit circuitry which half of the
buffer to read next.
Interrupts from the HDLC data link transmitter will appear on Transmitter
Interrupt [bit 14] in DL_CTRL_STAT [0x60]. Interrupts must be enabled to
appear on DL_INT by setting Enable HDLC Data Link = 1 in CONFIG_5.
100046C
Conexant
2-47