CN8223 Datasheet, PDF (141/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
4.0 Electrical and Mechanical Specifications
4.3 Timing
Figure 4-2. Line Interface Timing—DS1, E1, DS3, E3 External Framers
TXCKI,TXCKIHS
TXSYI
TXDATO (DS1/E1)
1
4
7
36
2
TXDATO (DS3/E3)
RXCKI,RXCKIHS
RXSYI
RXDATI
5
8
11 13
9 12
10
14
Table 4-4. Line Interface Timing—Internal Framers
Name
Interval
Description
ttxcki
1–6
Transmit Clock Period⁽¹⁾
ttxh
1–5
Transmit Clock Pulse Width High⁽²⁾
tcico
1–2
Transmit Clock In to Clock Out Delay (non-inverted)
tcod
2–3
Transmit Clock Out to Transmit Data Out
tcopn
2–4
Transmit Clock Out to Transmit Pos/Neg Out
trxcki
7–11
Receive Clock Period
trxh
7–10
Receive Clock Pulse Width High⁽²⁾
trdck
8–10
Receive Data Setup to Receive Clock Falling Edge
tckrd
10–12
Receive Data Hold after Receive Clock Falling Edge
tpnck
9–10
Receive Pos/Neg Setup to Receive Clock Falling Edge
tckpn
10–13
Receive Pos/Neg Hold after Receive Clock Falling Edge
NOTE(S): -
(1) _{Nominal clock periods are: E3 –29.1 ns STS-3c – 6.4 ns}
STS-1 –19.3 ns D3 – 22.4 ns
E4 –7.2 ns
(2) _{Duty cycle must be 45/55 at maximum input clock rate.}
Min
Max
6.4
—
2.9
—
2.6
10.0
1.0
4.0
0.1
1.0
6.4
—
2.9
—
1.0
—
0.8
—
0
—
3.5
—
100046C
Conexant
4-7