CN8223 Datasheet, PDF (60/161 Pages) Conexant Systems, Inc – ATM Transmitter/Receiver with UTOPIA Interface

2.0 Functional Description
2.6 ATM Cell Processing
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.6 ATM Cell Processing
The ATM cell processing block is located between the line framers and FIFO port
blocks of the CN8223 (see Figure 1-3). This functional block interfaces between
the octet data and cell data portions of the chip. The CN8223 supports cell
delineation via either PLCP or HEC alignment for DS1, E1, DS3, E3, E4, STS-1,
and STS-3c/STM-1 rates. At DS3 and E3 rates, all required stuffing functions are
supported.
2.6.1 Cell Generation for Transmit
Cell generation refers to the formatting of 53-octet ATM cells from 48- or
52-octet payload data from the FIFO interface for hand-off to the line framer
transmitter. The CN8223 provides modes that generate complete cells as well as
modes that pass entire 53- or 57-octet cells directly from the FIFO interface. Cell
modes and other per-port controls are in the four CELL_GEN_x registers
[0x04–0x07].
The generation process operates autonomously with a handshake protocol
through the FIFO interface. Cells are forwarded automatically to the line framer
for transmission.
When full ATM cell generation is performed, a 5-octet header is generated by
the CN8223. The VCI and other fields in the first 4 octets come from
microprocessor control registers. The HEC in octet 5 is calculated and inserted by
the CN8223. HEC coverage over 4-header octets (ATM) or 3-header octets
(SMDS/802.6) is selectable by HEC Coverage [bit 1] of CONFIG_3 [0x02]. The
remaining 48 octets are payload and are taken from the FIFO interface. The
CN8223 calculates and overwrites the CRC field to complete the 53-octet cell.
A cell-ready indication controls the cell generation process from the external
ATM interface circuit to the cell generation block. When the ATM interface
indicates that it has the first cell of a message ready, the cell generation block
begins formatting a non-idle cell for transmission using the octet data and cell
delineation control inputs at the interface. The cell generation circuitry
automatically generates idle cells until the external FIFO indicates that another
cell is ready for transfer. The header and payload for idle cells are programmable
via control registers. When the next cell is ready, the host presents the data and
cell delineation control inputs.
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Conexant
100046C