EPF10K30E Datasheet, PDF (9/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 1 shows a block diagram of the FLEX 10KE architecture. Each
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
Figure 1. FLEX 10KE Device Block Diagram
Embedded Array Block (EAB)
I/O Element
(IOE)
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE
IOE
Column
Interconnect
IOE
IOE
Row
Interconnect
Logic
Array
IOE
IOE
Logic Array
EAB
Logic Array
Block (LAB)
IOE
IOE
Logic Element (LE)
EAB
Local Interconnect
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
Embedded Array
FLEX 10KE devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.5 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
Altera Corporation
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