EPF10K30E Datasheet, PDF (57/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 24. LE Timing Microparameters (Part 2 of 2) Note (1)
Symbol
t_CLR
t_CH
t_CL
Parameter
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
Condition
Table 25. IOE Timing Microparameters Note (1)
Symbol
t_IOD
t_IOC
t_IOCO
t_IOCOMB
t_IOSU
t_IOH
t_IOCLR
t_OD1
t_OD2
t_OD3
t_XZ
t_ZX1
t_ZX2
t_ZX3
t_INREG
t_IOFD
t_INCOMB
Parameter
Conditions
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V_CCIO = 3.3 V
Output buffer and pad delay, slow slew rate = off, V_CCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V_CCIO = 3.3 V
IOE output buffer enable delay, slow slew rate = off, V_CCIO = 2.5 V
IOE output buffer enable delay, slow slew rate = on
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
Altera Corporation
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