EPF10K30E Datasheet, PDF (41/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
t_R
t_F
t _INDUTY
f _CLK1
f_CLK2
f _CLKDEV
t _INCLKSTB
t _LOCK
t _JITTER
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
Input deviation from user
specification in the MAX+PLUS II
software (1)
Input clock stability (measured
between adjacent clocks)
Time required for ClockLock or
ClockBoost to acquire lock (3)
Jitter on ClockLock or ClockBoost-
generated clock (4)
Condition
t _INCLKSTB < 100
t _INCLKSTB < 50
Min
Typ
40
25
Max
Unit
5
ns
5
ns
60
%
75
MHz
16
37.5
MHz
25,000 (2) PPM
100
ps
10
µs
250
ps
200 (4)
ps
t_OUTDUTY Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
60
%
Notes to tables:
(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The f_CLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during
device operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t_LOCK value is less than the time required for configuration.
(4) The t_JITTER specification is measured under long-term observation. The maximum value for t_JITTER is 200 ps if
t_INCLKSTB is lower than 50 ps.
I/O
Configuration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting V_CCIO to a different voltage than
V_CCINT. Its effect can be simulated in the Altera software via the Global
Project Device Options dialog box (Assign menu).
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