EPF10K30E Datasheet, PDF (19/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 9 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Figure 9. FLEX 10KE Carry Chain Operation (n-Bit Full Adder)
Carry-In
a1
LUT
Register
s1
b1
Carry Chain
LE1
a2
LUT
Register
s2
b2
Carry Chain
LE2
an
bn
Altera Corporation
LUT
Carry Chain
LUT
Carry Chain
Register
sn
LEn
Register
Carry-Out
LEn + 1
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