EPF10K30E Datasheet, PDF (60/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 28. Interconnect Timing Microparameters Note (1)
Symbol
Parameter
Conditions
t_DIN2IOE
t_DIN2LE
t_DCLK2IOE
t_DCLK2LE
t_DIN2DATA
t_SAMELAB
t_SAMEROW
t_SAMECOLUMN
t_DIFFROW
t_TWOROWS
t_LEPERIPH
t_LABCARRY
t_LABCASC
Delay from dedicated input pin to IOE control input
(7)
Delay from dedicated input pin to LE or EAB control input
(7)
Delay from dedicated clock pin to IOE clock
(7)
Delay from dedicated clock pin to LE or EAB clock
(7)
Delay from dedicated input or clock to LE or EAB data
(7)
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)
same row
Routing delay for an LE driving an IOE in the same column
(7)
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)
Routing delay for an LE driving a control signal of an IOE via the peripheral (7)
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Table 29. External Timing Parameters
Symbol
t_DRR
t_INSU
t_INH
t_OUTCO
t_PCISU
t_PCIH
t_PCICO
Parameter
Conditions
Register-to-register delay via four LEs, three row interconnects, and four local (8)
interconnects
Setup time with global clock at IOE register
(9)
Hold time with global clock at IOE register
(9)
Clock-to-output delay with global clock at IOE register
(9)
Setup time with global clock for registers used in PCI designs
(9),(10)
Hold time with global clock for registers used in PCI designs
(9),(10)
Clock-to-output delay with global clock for registers used in PCI designs
(9),(10)
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