EPF10K30E Datasheet, PDF (33/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Tables 8 and 9 list the sources for each peripheral control signal, and show
how the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. The tables also show the rows that can drive
global signals.
Table 8. Peripheral Bus Sources for EPF10K30E, EPF10K50E & EPF10K50S Devices
Peripheral
Control Signal
OE0
OE1
OE2
OE3
OE4
OE5
CLKENA0/CLK0/GLOBAL0
CLKENA1/OE6/GLOBAL1
CLKENA2/CLR0
CLKENA3/OE7/GLOBAL2
CLKENA4/CLR1
CLKENA5/CLK1/GLOBAL3
EPF10K30E
Row A
Row B
Row C
Row D
Row E
Row F
Row A
Row B
Row C
Row D
Row E
Row F
EPF10K50E
EPF10K50S
Row A
Row B
Row D
Row F
Row H
Row J
Row A
Row C
Row E
Row G
Row I
Row J
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