EPF10K30E Datasheet, PDF (40/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Tables 12 and 13 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 12. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices
Symbol
Parameter
t_R
t_F
t _INDUTY
f _CLK1
f_CLK2
f _CLKDEV
t _INCLKSTB
t _LOCK
t _JITTER
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
Input deviation from user
specification in the MAX+PLUS II
software (1)
Input clock stability (measured
between adjacent clocks)
Time required for ClockLock or
ClockBoost to acquire lock (3)
Jitter on ClockLock or ClockBoost-
generated clock (4)
Condition
t_INCLKSTB < 100
t_INCLKSTB < 50
Min
Typ
40
25
16
t_OUTDUTY Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
Max
Unit
5
ns
5
ns
60
%
180
MHz
90
MHz
25,000 (2) PPM
100
ps
10
µs
250
ps
200 (4)
ps
60
%
40
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