EPF10K30E Datasheet, PDF (2/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 2. FLEX 10KE Device Features
Feature
Typical gates (1)
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
EPF10K100E (2)
100,000
257,000
4,992
12
49,152
338
EPF10K130E
130,000
342,000
6,656
16
65,536
413
EPF10K200E
EPF10K200S
200,000
513,000
9,984
24
98,304
470
Note to tables:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
(2) New EPF10K100B designs should use EPF10K100E devices.
...and More
Features
– Fabricated on an advanced process and operate with a 2.5-V
internal supply voltage
– In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
– ClockLock^TM and ClockBoost^TM options for reduced clock
delay/skew and clock multiplication
– Built-in low-skew clock distribution trees
– 100% functional testing of all devices; test vectors or scan chains
are not required
– Pull-up on I/O pins before and during configuration
■ Flexible interconnect
– FastTrack^® Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
– Tri-state emulation that implements internal tri-state buses
– Up to six global clock signals and four global clear signals
■ Powerful I/O pins
– Individual tri-state output enable control for each pin
– Open-drain option on each I/O pin
– Programmable output slew-rate control to reduce switching
noise
– Clamp to V_CCIO user-selectable on a pin-by-pin basis
– Supports hot-socketing
2
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