EPF10K30E Datasheet, PDF (31/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 15. FLEX 10KE Bidirectional I/O Registers
Row and Column 2 Dedicated
Interconnect Clock Inputs
4 Dedicated Peripheral
Inputs
Control Bus
2
4
12
VCC
OE Register
DQ
ENA
CLRN
VCC
OE[7..0]
Chip-Wide
Reset
(1)
Programmable Delay
Chip-Wide
Output Enable
VCC
CLK[1..0]
CLK[3..2]
VCC
ENA[5..0]
VCC
CLRN[1..0]
Output Register (2)
DQ
ENA
CLRN
Open-Drain
Output
Slew-Rate
Control
VCC
Chip-Wide
Reset _{Input Register (2)}
DQ
ENA
CLRN
Chip-Wide
Reset
Note:
(1) All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer
on the input path.
Altera Corporation
31