EPF10K30E Datasheet, PDF (56/100 Pages) Altera Corporation – Embedded Programmable Logic Device

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Dedicated
Clock
OE Register
PRN
DQ
CLRN
Output Register
PRN
DQ
t_XZBIDIR
t_ZXBIDIR
t_OUTCOBIDIR
Bidirectional
Pin
CLRN
t_INSUBIDIR
t_INHBIDIR
Input Register
PRN
DQ
CLRN
Tables 24 through 28 describe the FLEX 10KE device internal timing
parameters. Tables 29 through 30 describe the FLEX 10KE external timing
parameters and their symbols.
Table 24. LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol
t_LUT
t_CLUT
t_RLUT
t_PACKED
t_EN
t_CICO
t_CGEN
t_CGENR
t_CASC
t_C
t_CO
t_COMB
t_SU
t_H
t_PRE
Parameter
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
LE register hold time for data and enable signals after clock
LE register preset delay
Condition
56
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