AK4753 Datasheet, PDF (81/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ Stop of Clock
When the AK4753 is not used, the master clock can be stopped.
1. PLL Master mode
PWXTL bit
PMPLL bit
(Addr:04H, D2,D7)
External MCKI
(1)
(2)
Input
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1) Addr:04H, Data:00H
(2) Stop an external MCKI
Figure 82. Clock Stopping Sequence (1)
<Example>
(1) Power down Cristal Oscillator and PLL: PWXTL, PMPLL bits = “1” → “0”
(2) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
(Addr:04H, D7)
External BICK
External LRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:04H, Data:00H
(2) Stop the external clocks
Figure 83. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks.
3. EXT Slave Mode
External MCKI
Input
External BICK
Input
External LRCK
Input
(1)
Example
(1)
Audio I/F Format :MSB justified
Input MCKI frequency:256fs
(1)
(1) Stop the external clocks
Figure 84. Clock Stopping Sequence (3)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
MS1311-E-00
- 81 -
2011/07