AK4753 Datasheet, PDF (53/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ Serial Control Interface (I2C-bus Control: EXTEE pin = “L”)
The AK4753 supports the fast-mode I²C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be
connected to (DVDD+0.3)V or less voltage.
1. WRITE Operations
Figure 66 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 72). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction
bit (R/W). The most significant seven bits of the slave address are fixed as “0010010” (Figure 67). If the slave address
matches that of the AK4753, the AK4753 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 73). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates that the write
operation is to be executed.
The second byte consists of the control register address of the AK4753. The format is MSB first, and those most
significant 1bit is fixed to zero (Figure 68). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 69). The AK4753 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 72).
The AK4753 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4753
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating
the write cycle after the first data byte is transferred. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 7DH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 74) except for the START and STOP
conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 66. Data Transfer Sequence at I²C Bus Mode
0
0
1
0
0
1
0
R/W
Figure 67. The First Byte
0
A6
A5
A4
A3
A2
A1
A0
Figure 68. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 69. The Third Byte
MS1311-E-00
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2011/07