AK4753 Datasheet, PDF (76/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
1. Grounding and Power Supply Decoupling
The AK4753 requires careful attention to power supply and grounding arrangements. If AVDD and DVDD are supplied
separately, the power-up sequence is not critical. VSS1 and VSS2 of the AK4753 must be connected to the analog
ground plane. System analog ground and digital ground must be connected together near to where the supplies are
brought onto the printed circuit board. Decoupling capacitors must be as near to the AK4753 as possible, with the small
value ceramic capacitor being the nearest.
2. Internal Regulated Voltage Power Supply
The input voltage to the REG pin is used as power supply (typ. 1.8V) for the internal digital circuit. A 2.2μF±50%
ceramic capacitor connected between the REG and VSS2 pins eliminates the effects of high frequency noise. This
capacitor in particular should be connected as close as possible to the pin. No load current may be drawn from the REG
pin. All digital signals, especially clocks, should be kept away from the REG pin in order to avoid unwanted coupling
into the AK4753.
3. Voltage Reference
VCOM is a signal ground of this chip. A 2.2μF±50% ceramic capacitor connected between this pin and the VSS1 pin
eliminates the effects of high frequency noise. This capacitor in particular should be connected as close as possible to
the pin. No load current may be drawn from the VCOM pin. All digital signals, especially clocks, must be kept away
from the VCOM pin in order to avoid unwanted coupling into the AK4753.
4. Analog Inputs
The line inputs are single-ended. The input signal range scales with nominally at typ. 2.64Vpp (0.8 x AVDD), centered
around the internal signal ground (AVDD/2). Usually the input signal is AC coupled using a capacitor. The cut-off
frequency is fc = 1/ (2πRC). The AK4753 can accept input voltages from VSS1 to AVDD.
5. Analog Outputs
The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH
(@24-bit) and a negative full scale for 800000H (@24-bit). The ideal output is VCOM voltage for 000000H (@24-bit).
The line outputs are single-ended or differential and centered at AVDD/2.
MS1311-E-00
- 76 -
2011/07