AK4753 Datasheet, PDF (62/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
Addr Register Name
D7
D6
D5
D4
D3
03H Mode Setting 2 BCKO
M/S
BCKP MSBS
0
R/W
R/W
R/W
R/W
R/W
RD
Default
1
0
0
0
0
D2
DIF2
R/W
0
D1
DIF1
R/W
1
DIF2-0: Audio Interface Format (Table 14)
Default: “011” (I²S)
MSBS: LRCK Polarity at DSP Mode (Table 15, Table 16, Table 17)
0: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
1: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
BCKP: BICK Polarity at DSP Mode (Table 15, Table 16, Table 17)
0: SDTI is latched by the falling edge (“↓”) of BICK. (default)
1: SDTI is latched by the rising edge (“↑”) of BICK.
M/S: Master / Slave Mode Setting
0: Slave Mode (default)
1: Master Mode
BCKO: BICK Output Frequency Select at Master Mode (Table 8)
D0
DIF0
R/W
1
Addr Register Name D7
D6
D5
D4
D3
D2
D1
D0
04H
Power
Management
PMPLL
0
PMLO2 PMLO1 PMDIG PWXTL
0
PMADC
R/W
R/W
RD
R/W
R/W
R/W
R/W
RD
R/W
Default
0
0
0
0
0
0
0
0
PMADC: ADC Power Management
0: Power-down (default)
1: Power-up
PWXTL: The power management of the crystal oscillation circuit
0: Power OFF (default)
1: Power ON
PMDIG: DSP & DAC Digital Power Management
0: Power-down (default)
1: Power-up
PMLO1: Line Out1 Power Management and External Mute Control
0: Power-down (default)
1: Power-up
PMLO2: Line Out2 Power Management and External Mute Control
0: Power-down (default)
1: Power-up
PMPLL: PLL Power Management
0: EXT Mode and Power-Down (default)
1: PLL Mode and Power-up
MS1311-E-00
- 62 -
2011/07