AK4753 Datasheet, PDF (79/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
3. EXT Slave Mode
Power Supply
PDN pin
Regulator
VCOM
MCKI pin
BICK pin
LRCK pin
(1)
(2)
(4)
1ms(max)
(3)
Input
Example:
Audio I/F Format: MSB justified
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
Regulator, VCOM Power-up
(3) Addr:02H, Data:00H
Addr:03H, Data:02H
MCKI, BICK and LRCK input
Figure 79. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 10ms or more is needed to reset the AK4753.
(2) Power Up VCOM and Regulator
Power up time is 1ms (max). To write register is forbidden during this period.
(3) FS1-0, BCKP, MSBS and DIF2-0 bits must be set during this period.
(4) Normal operation starts after the MCKI, LRCK and BICK are supplied.
4. EXT Master Mode
Power Supply
PDN pin
Regulator
VCOM
PWXTL bit
(Addr:04H, D2)
XTI/MCKI pin
(1)
(2)
1ms(max) (3)
M/S bit
(Addr:03H, D6)
BICK pin
LRCK pin
Example:
Audio I/F Format: MSB justified
Input MC KI frequency: 256fs
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(4)
Input
Regulator, VCOM Power-up
(3) Addr:02H, Data:00H
Addr:03H, Data:82H
Output
Figure 80. Clock Set Up Sequence (4)
(4) Addr:03H, Data:C2H
BICK and LRCK output
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 10ms or more is needed to reset the AK4753.
(2) Power Up VCOM and Regulator
Power up time is 1ms (max). To write register is forbidden during this period.
(3) FS1-0, BCKO, BCKP, MSBS and DIF2-0 bits must be set during this period.
(4) M/S bit should be set to “1” after the crystal oscillator becomes stable or MCKI is supplied from an external
source. Then LRCK and BICK are output.
MS1311-E-00
- 79 -
2011/07