AK4753 Datasheet, PDF (78/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
2. PLL Slave Mode (LRCK or BICK pin)
Power Supply
PDN pin
Regulator
VCOM
PMPLL bit
(Addr:04H, D7)
LRCK pin
BICK pin
(1)
(2)
1ms(max) (3)
Internal Clock
(4)
Input
40ms (max)
Example:
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
4fs₍₁o₎f _{Power Supply & PDN pin = “L” Æ “H”}
Regulator, VCOM Power-up
(5)
Output
(3) Addr:02H, Data:83H
Addr:03H, Data:02H
(4) Addr:04H, Data:80H
Figure 78. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 10ms or more is needed to reset the AK4753.
(2) Power Up VCOM and Regulator
Power up time is 1ms (max). To write register is forbidden during this period.
(3) FS3-2, PLL3-0, BCKP, MSBS and DIF2-0 bits must be set during this period.
(4) PWXTL and PMPLL bits change from “0” to “1”. Then PLL starts after PLL reference clock (LRCK or
BICK pin) is supplied from an external source. PLL lock time is 40ms (max) when LRCK is a PLL reference
clock. PLL lock time is 4ms (max) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
MS1311-E-00
- 78 -
2011/07