AK4753 Datasheet, PDF (19/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ System Clock
There are the following four methods to interface with external devices. (Table 1, Table 2)
Mode
PMPLL bit
M/S bit
PLL Master Mode
1
1
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
1
0
EXT Slave Mode
0
0
EXT Master Mode
0
1
Table 1. Clock Mode Setting (x: Don’t care)
PLL3-0 bits
Table 4
Table 4
x
x
Figure
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Mode
XTI/MCKI pin
BICK pin
PLL Master Mode
Selected by PLL3-0 bits
Output
(Selected by BCKO bit)
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
GND
Input
(Selected by PLL3-0 bits)
EXT Slave Mode
Selected by FS1-0 bits
Input
(≥ 32fs)
EXT Master Mode
Selected by FS1-0 bits
Output
(Selected by BCKO bit)
Table 2. Clock pins state in Clock Mode
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When
the AK4753 is in power-down mode (PDN pin = “L”) and when exits reset state, the AK4753 is in slave mode. After
exiting reset state, the AK4753 goes to master mode by changing M/S bit = “1”.
When the AK4753 is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The
LRCK and BICK pins of the AK4753 must be pulled-down or pulled-up by the resistor (about 100kΩ) externally to
avoid the floating state.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
(default)
MS1311-E-00
- 19 -
2011/07