AK4753 Datasheet, PDF (13/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

CONFIDENTIAL
[AK4753]
Parameter
Symbol
min
typ
max
Control Interface Timing (I²C bus-slave): SCL, SDA pins (Note 19)
SCL Clock Frequency
fSCL1
-
-
400
Bus Free Time Between Transmissions
tBUF1
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD1:STA 0.6
-
-
Clock Low Time
tLOW1
1.3
-
-
Clock High Time
tHIGH1
0.6
-
-
Setup Time for Repeated Start Condition
tSU1:STA 0.6
-
-
SDA Hold Time from SCL Falling (Note 20)
tHD1:DAT
0
-
-
SDA Setup Time from SCL Rising
tSU1:DAT 0.1
-
-
Rise Time of Both SDA and SCL Lines
tR1
-
-
0.3
Fall Time of Both SDA and SCL Lines
tF1
-
-
0.3
Capacitive Load on Bus
Cb1
-
-
400
Setup Time for Stop Condition
tSU1:STO 0.6
-
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP1
0
-
50
EEP-ROM Control Interface Timing (I²C bus-master): EESCL, EESDA pins (Note 19)
EESCL Clock Frequency
fSCL2
200
280
400
Bus Free Time Between Transmissions
tBUF2
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA2 0.6
-
-
Clock Low Time
tLOW2
1.3
-
-
Clock High Time
tHIGH2
0.6
-
-
Setup Time for Repeated Start Condition
tSU2:STA 0.6
-
-
EESDA Hold Time from EESCL Falling (Note 20) tHD2:DAT
0
-
0.9
EESDA Setup Time from EESCL Rising
tSU2:DAT 0.1
-
-
Rise Time of Both EESDA and EESCL Lines
tR2
-
-
0.3
Fall Time of Both EESDA and EESCL Lines
tF2
-
-
0.3
Capacitive Load on Bus
Cb2
-
-
400
Setup Time for Stop Condition
tSU2:STO 0.6
-
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP2
0
-
50
Power-down & Reset Timing
PDN Pulse Width (Note 21)
Note 19. I²C-bus is a trademark of NXP B.V.
tPD
10
-
-
Note 20. Data must be held long enough to bridge the 300ns-transition time of SCL and EESCL.
Note 21. The AK4753 can be reset by the PDN pin = “L”.
Units
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
μs
ns
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
μs
ns
ms
MS1311-E-00
- 13 -
2011/07