AK4753 Datasheet, PDF (77/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
CONTROL SEQUENCE
■ Clock Setup
When any circuits of the AK4753 are powered-up, the clocks must be supplied.
1. PLL Master Mode
Power Supply
PDN pin
Regulator
VCOM
PWXTL bit
PMPLL bit
(Addr:04H, D2,D7)
XTI/MCKI pin
(1)
(2)
1ms(max) (3)
M/S bit
(Addr:01H, D3)
BICK pin
LRCK pin
(4)
Input
4ms (max)
(5)
Output
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
Regulator, VCOM Power-up
(3) Addr:02H, Data:F4H
Addr:03H, Data:C2H
(4) Addr:04H, Data:84H
BICK and LRCK output
Figure 77. Clock Set Up Sequence (1)
<Example>
(1)After Power Up, PDN pin “L” Æ “H”
“L” time of 10ms or more is needed to reset the AK4753.
(2)Power Up VCOM and Regulator
Power up time is 1ms (max). To write register is forbidden during this period.
(3)FS3-0, PLL3-0, BCKO, BCKP, MSBS and DIF2-0 bits must be set during this period.
(4)PWXTL and PMPLL bits change from “0” to “1”. Then PLL starts after the crystal oscillator becomes stable
or XTI/MCKI pin is supplied from an external source. PLL lock time is 4ms (max).
(5)The AK4753 starts to output the LRCK and BICK clocks after the PLL became stable. Then normal
operation starts.
MS1311-E-00
- 77 -
2011/07