AK4753 Datasheet, PDF (22/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ PLL Un-Lock
1. PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the BICK and LRCK pins go to “L” before the PLL goes to lock state after PMPLL bit = “0” →“1”
(Table 7). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs. When sampling frequency is changed, the BICK and LRCK pins do not output
irregular frequency clocks but go to “L” by setting PMPLL bit to “0”.
PLL State
PMPLL bit “0” Æ “1”
BICK pin
“L” Output
LRCK pin
“L” Output
PLL Unlock (Except for the above)
Not fixed
Not fixed
PLL Lock
Table 8
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 22.5792MHz, 24MHz or 24.576MHz) is input to the
XTI/MCKI pin or the crystal oscillator circuit is used, the BICK and LRCK clocks are generated by an internal PLL
circuit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table 8).
AK4753
MCKI
BICK
LRCK
11.2896MHz, 12MHz, 12.288MHz
22.5792MHz, 24MHz, 24.576MHz
DSP
32fs, 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 20. PLL Master Mode (External Clock Mode)
AK4753
XTO
X’tal
11.2896MHz, 12MHz, 12.288MHz
22.5792MHz, 24MHz, 24.576MHz
XTI
BICK
LRCK
32fs, 64fs
1fs
DSP
BCLK
LRCK
SDTI
SDTO
Figure 21. PLL Master Mode (X’tal Mode)
BCKO bit
BICK Output Frequency
0
32fs
1
64fs
(default)
Table 8. BICK Output Frequency at Master Mode
MS1311-E-00
- 22 -
2011/07