AK4753 Datasheet, PDF (23/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the BICK or LRCK pin. Required clock for the AK4753
is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
Sampling frequency corresponds to a range from 7.35kHz to 48kHz by changing FS3-0 bits (Table 6).
AK4753
DSP
MCKI
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 22. PLL Slave Mode (PLL Reference Clock: BICK pin)
AK4753
DSP
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 23. PLL Slave Mode (PLL Reference Clock: LRCK pin)
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4753 changes to EXT mode. Master clock is input from the XTI/MCKI pin, the
internal PLL circuit is not operated. This mode is compatible with I/F of a normal audio CODEC. The clocks required
to operate the AK4753 are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI)
should be synchronized with LRCK. The phase between these clocks is not important. The input frequency of MCKI is
selected by FS1-0 bits (Table 9).
Mode
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
512fs
7.35kHz ∼ 26kHz
Table 9. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
MS1311-E-00
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2011/07