AK4753 Datasheet, PDF (54/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4753. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data
word. After receiving each data packet the internal address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 7DH prior to generating stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK4753 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4753 has an internal address counter that maintains the address of the last accessed word incremented by one.
Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4753 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the
AK4753 ceases the transmission.
S
T
A
R/W="1"
R
T
SDA
Slave
S _Address
A
C
K
Data(n)
Data(n+1)
Data(n+2)
MA
MA
MA
AC
AC
AC
S
T
K
S
T
K
S
T
K
E
E
E
R
R
R
Figure 70. Current Address Read
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
S
T
K
E
S
T
E
C
K
R
R
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave
address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start
request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is
acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The
AK4753 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master
does not generate an acknowledge but generates a stop condition instead, the AK4753 ceases the transmission.
S
T
A
R/W="0"
R
T
S
T
A
R/W ="1"
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
A
A
A
MA
MA
C
K
C
K
C
K
AC
S
T
K
A
S
T
C
K
E
E
R
R
Figure 71. Random Address Read
S
T
O
P
Data(n+x)
P
MA
MN
A
S
T
C
K
A
S
T
A
C
E
EK
R
R
MS1311-E-00
- 54 -
2011/07