AK4753 Datasheet, PDF (80/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ DAC Outputs
FS3-0 bits
(Addr:02H, D7-4)
0000
(1)
1111
Siglnal Path
(Addr:01H)
00H
(2)
L/R7-0 bits
(Addr:05H&06H, D7-0)
FFH
(3)
Gain Setting
(Addr:07H)
XX....X
(4)
DSP1 Limiter Control _XX....X
(Addr:08-0AH)
(5)
DSP2 Limiter Control _XX....X
(Addr:0B-0DH)
(6)
DSP1 Filter Coef
(Addr:0E-17H)
XX....X
(7)
DSP1 EQ Coef
(Addr:18-45H)
XX....X
(8)
DSP2 Filter Coef
(Addr:46-4FH)
XX....X
(9)
DSP2 EQ Coef
(Addr:50-7DH)
XX....X
(10)
E0H
00H
XX....X
XX....X
XX....X
XX....X
XX....X
XX....X
XX....X
Limiter State
Limiter Disable
Limiter Enable
PMLO1/2 bits
PMDIG bit
PMADC bit
(Addr:04H, D5-4,D3,D0)
MUTEN pin
(11)
Mute On
4ms (typ)
Mute Off
Limiter Disable
(12)
Mute On
LOUT1/2 pins
MOUT+/- pins
Normal Output
Example:
PLL Master Mode
Audio I/F Format: MSB justified
Input MCKI frequency:11.2896MHz
Sampling Frequency: 44.1kHz
Input Signal Setting: Analog
DAC Output Configuration: 2.1ch mode
Digital Volume: −30dB
Limiter and EQ: Enable
(1) Addr:02H, Data:F4H
(2) Addr:01H, Data:E0H
(3) Addr:05H &06H, Data:00H
(4) Addr:07H, Data:55H
(5) Addr:08H, Data:01H
Addr:09H, Data:1EH
Addr:0AH, Data:30H
(6) Addr:0BH, Data:01H
Addr:0CH, Data:1EH
Addr:0DH, Data:30H
(7) Addr:0EH, Data:03H
(8) Addr:18H, Data:1FH
(9) Addr:46H, Data:01H
(10) Addr:50H, Data:1FH
(11) Addr:04H, Data:BDH
Playback
(12) Addr:04H, Data:84H
Figure 81. DAC Output Sequence
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4753 is PLL mode, DAC of (11) must be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of Analog Input Æ DAC Æ 2.1ch Output and the ALMT1/2 bits: SEL1-0 bits = “00” Æ “00”,
SPC1-0 bits = “00” Æ “10”, ALMT1/2 bits = “0” → “1”
(3) Set up the output digital volume (Addr = 05H, 06H)
After DAC is powered-up, the digital volume changes from default value (Mute) to the register setting value
by the soft transition.
(4) Set up the Pre-Gain and Post-Gain: 1PREG1-0 bits = 2PREG1-0 bits = “00” → “01”, 1PSTG1-0 bits =
2PSTG1-0 bits = “00” → “01”
(5) Set up 1LMTH1-0, 1LMAT1-0, 1RGAIN1-0, 1ZELMN, 1LFSTN, 1ZTM1-0, 1WTM2-0 and 1RFSN1-0 bits
(Addr = 08H, 09H) and the REF value (Addr: 0AH) for Limiter of DSP1
Set up 2LMTH1-0, 2LMAT1-0, 2RGAIN1-0, 2ZELMN, 2LFSTN, 2ZTM1-0, 2WTM2-0 and 2RFSN1-0 bits
(Addr = 0BH, 0CH) and the REF value (Addr: 0DH) for Limiter of DSP2
(6) Set up Coefficient of LPF/HPF for DSP1 (Addr: 0EH ~ 17H)
(7) Set up Coefficient of EQ for DSP1 (Addr: 18H ~ 45H)
(8) Set up Coefficient of LPF/HPF for DSP2 (Addr: 46H ~ 4FH)
(9) Set up Coefficient of EQ for DSP2 (Addr: 50H ~ 7DH)
(10) Power Up the ADC, DSP, DAC and Line-Amp: PMADC = PMDIG = PMLO1 = PMLO2 bits = “0” → “1”
When ALMT1 bit or ALMT2 bit = “1”, Limiter operation starts from the gain set by L/R7-0 bits after the
initialization cycle of ADC (1059/fs = 24ms @fs=44.1kHz).
(11) Power Down the ADC, DSP, DAC and Line-Amp: PMADC = PMDIG = PMLO1 = PMLO2 bits = “1” →
“0”
MS1311-E-00
- 80 -
2011/07