AK4753 Datasheet, PDF (61/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ Register Definitions of Fundamental Function
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H SAR Control CTM1 CTM0 SA2SEL SA2 PMSAR
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
RD
RD
RD
Default
0
0
0
0
0
0
0
0
PMSAR: SAR ADC Power Management
0: Power-down (default)
1: Power-up
SA2: SAIN2 Enable
0: SAIN2 Disable (default)
1: SAIN2 Enable
SA2SEL: SAIN2 Output Configuration setting (Table 42)
0: Setting for DSP1 (default)
1: Setting for DSP2
CTM1-0: Cycle Time setting (Table 44)
Default: “00”
Addr Register Name D7
D6
D5
D4
D3
D2
D1
01H Signal Path ALMT1 ALMT2 SPC1
SPC0
0
SEL1
0
R/W
R/W
R/W
R/W
R/W
RD
R/W
RD
Default
0
0
0
0
0
0
0
SEL1-0: DSP Input setting (Table 18)
00: Analog-in (default)
01: Digital-in
10: Mix
SPC1-0: Line Output Configuration setting (Table 20, Table 21, Table 22, Table 23)
Those bits select the output mode to 2-channels mode, 2.1-channels mode, and 4-channels mode.
Default: “00”
ALMT2: DSP2 Limiter Enable
0: Limiter Disable (default)
1: Limiter Enable
ALMT1: DSP1 Limiter Enable
0: Limiter Disable (default)
1: Limiter Enable
D0
SEL0
R/W
0
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
02H Mode Setting 1 FS3
FS2
FS1
FS0
PLL3 PLL2 PLL1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
PLL3-0: PLL Reference Clock Select (Table 4)
Default: “0000” (LRCK pin)
FS3-0: Sampling Frequency Select (Table 5, Table 6) and MCKI Frequency Select (Table 9, Table 11)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
D0
PLL0
R/W
0
MS1311-E-00
- 61 -
2011/07