AK4753 Datasheet, PDF (21/85 Pages) Asahi Kasei Microsystems – 2-in, 4-out CODEC with DSP Functions

[AK4753]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit = “1”, the built-in high precision PLL works according to the clock which is set by FS3-0 bits and
PLL3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4753 is supplied to a stable clock after PLL is
powered-up (PMPLL bit = “0” →“1”) or sampling frequency changes.
1. PLL Mode setting
Mode
0
1
2
3
4
5
6
7
8
Others
PLL3
bit
0
0
0
0
0
0
0
1
1
PLL2 PLL1 PLL0
bit bit bit
0
0
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
1
0
1
Others
PLL Reference
Clock Input Pin
Input
Frequency
FLT pin
PLL Lock
Rp, Cp
Time
Rp[Ω] Cp[F] ^(max)
LRCK pin
1fs
10k 100n 40 ms (default)
BICK pin
32fs
10k 4.7n
4 ms
BICK pin
64fs
10k 4.7n
4 ms
XTI/MCKI pin 11.2896MHz 10k 4.7n
4 ms
XTI/MCKI pin 12.288MHz 10k 4.7n
4 ms
XTI/MCKI pin 12MHz
10k 4.7n
4 ms
XTI/MCKI pin 24MHz
10k 4.7n
4 ms
XTI/MCKI pin 22.5792MHz 10k 4.7n
4 ms
XTI/MCKI pin 24.576MHz 10k 4.7n
4 ms
N/A
(*fs: Sampling Frequency, N/A: Not Available)
Table 4. PLL Mode Setting
2. Sampling Frequency setting in PLL Mode
In the case of PLL2 bit = “1”, and the reference clock is input to the XTI/MCKI pin or the crystal oscillator circuit is
used, the sampling frequency can be set according to Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
(Reference Clock = XTI/MCKI pin) (N/A: Not Available)
Table 5. Sampling Frequency Setting (PMPLL bit = “1”)
In the case of PLL2 bit = “0” and the reference clock is input to the LRCK or BICK pins, the sampling frequency is set
by FS3 and FS2 bits according to Table 6.
Mode
0
1
2
Others
FS3 bit FS2 bit FS1 bit FS0 bit
Sampling Frequency
Range
0
0
x
x
7.35kHz ≤ fs ≤ 12kHz (default)
0
1
x
x
12kHz < fs ≤ 24kHz
1
0
x
x
24kHz < fs ≤ 48kHz
Others
N/A
(PLL Reference: Clock: LRCK or BICK pin) (x: Don’t care, N/A: Not Available)
Table 6. Sampling Frequency Setting (PLL2 bit = “0” and PMPLL bit = “1”)
MS1311-E-00
- 21 -
2011/07