AK8854VQ Datasheet, PDF (78/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
PGA Control 1 Register (R/W) [Sub Address 0x0E], for PGA gain setting
Sub Address 0x0E
bit 7
bit 6
Reserved PGA_6
Default Value
0
0
bit 5
PGA_5
1
bit 4
PGA_4
1
bit 3
PGA_3
1
bit 2
PGA_2
1
Default Value: 0x3E
bit 1
bit 0
PGA_1
PGA_0
1
0
PGA Control 1 Register Definition
Bit
Register
Name
bit 0 PGA_0
~
~
PGA Gain Set
bit 6 PGA_6
bit 7 Reserved Reserved
R/W Definition
R/W PGA gain setting, in steps of approx. 0.1 dB
R/W Reserved
PGA Control 2 Register (R/W) [Sub Address 0x0F], for PGA gain setting
Sub Address 0x0F
bit 7
bit 6
Reserved PGA_6
Default Value
0
0
bit 5
PGA_5
1
bit 4
PGA_4
1
bit 3
PGA_3
1
bit 2
PGA_2
1
Default Value: 0x3E
bit 1
bit 0
PGA_1
PGA_0
1
0
PGA Control 2 Register Definition
Bit
Register
Name
bit 0 PGA_0
~
~
PGA Gain Set
bit 6 PGA_6
bit 7 Reserved Reserved
R/W Definition
R/W PGA gain setting, in steps of approx. 0.1 dB
R/W Reserved
MS0973-E-01
78
2008/07