AK8854VQ Datasheet, PDF (49/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
7.17 Output interface
7.17.1 656 interface
7.17.1.1 Line-locked and frame-locked clock modes
In both of these modes, the decoded data output is compliant with ITU-R BT.656, which
requires the following sample and line numbers.
Samples per line: 858 (525 line) or 864 (625 line)
Lines per frame: 525 or 625
It may not be possible, however, to meet these requirements if the input signal quality is poor.
In the AK8854, PLL is locked to the input signal and output-stage buffers absorb input signal jitter, but if
the jitter is excessive PLL tracking may be impracticable and ITU-R BT.656 compliance may thus be
lost.
In such cases, the following processing can be applied via the indicated register settings.
(a) Line drop/repeat processing
A line drop or line repeat will result in output signals with 524/624 or 526/626 lines per frame,
respectively. Line drop/repeat processing may be performed at any line in the frame.
(b) Pixel drop/repeat processing
A pixel drop or pixel repeat will result in output signals less or more than the required 858/864
samples in the last line of the frameor field, respectively.
Note: In the event of output-stage buffer failure, line drop/repeat processing will be performed
even if the register setting is for pixel drop/repeat processing.
ERRHND-bits: Settings for line and pixel drop/repeat processing
ERRHND-bits
Processing mode
[00]
Line Drop / Line Repeat
[01]
Pixel Drop / Pixel Repeat by Field
[10]
Pixel Drop / Pixel Repeat by Frame
[11]
Reserved
Notes
Default
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MS0973-E-01
49
2008/07