AK8854VQ Datasheet, PDF (31/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

Clamp Timing Pulse
[AK8854VQ]
CLPSTAT[1:0] = 00
CLPSTAT[1:0] = 01
CLPSTAT[1:0] = 11
CLPSTAT[1:0] = 10
CLPWIDTH[1:0]
1/128H delay
1/128H advance
2/128H advance
Sync tip/ middle/ bottom clamp
CLPSTAT[1:0] = 00
BCLPSTAT[2:0] = 000
CLPSTAT[1:0] =10
BCLPSTAT[2:0] = 000
CLPSTAT[1:0] =10
BCLPSTAT[2:0] = 111
CLPSTAT[1:0] =10
BCLPSTAT[2:0] = 000
CLPWIDTH[1:0]
2/128H advance
3/128H advance
2/128H advance
Back porch clamp
○CLPG[1:0]: Set the current value of fine clamp in analog block.
CLPG[1:0]-bit
Clamp current value
Notes
[00]
Min.
[01]
Middle 1 (Default)
[10]
Middle 2
[11]
Max.
Sub-address 0x02_[1:0]
Middle 1 < Middle 2
○UDG[1:0]ɿSet the current value of rough clamp in analog block.
UDG[1:0]-bit
Clamp current value
Notes
[00]
Min. (Default)
[01]
Middle 1
[10]
Middle 2
[11]
Max.
Sub-address 0x02_[3:2]
Middle 1 < Middle 2
Its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp), as
described in Sec. 7.20 below.
MS0973-E-01
31
2008/07