AK8854VQ Datasheet, PDF (65/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
AFE Control Register 2(R/W) [Sub Address 0x02], for analog front end
Sub Address 0x02
bit 7
bit 6
Reserved Reserved
Default Value
0
0
bit 5
Reserved
0
bit 4
YPBPRCP
0
bit 3
UDG1
0
bit 2
UDG0
0
Default Value: 0x01
bit 1
bit 0
CLPG1 CLPG0
0
1
AFE Control Register 2 Definition
Bit
Register
Name
bit 0 CLPG 0
~
~
bit 1 CLPG1
Clamp Gain
bit 2 UDG 0
~
~
bit 3 UDG 1
Up Down Gain
bit 4 YPBPRCP YPbPr Clamp
bit 5
~ Reserved
bit 7
Reserved
R/W
R/W
R/W
R/W
R/W
Definition
Set the current value of fine clamp in analog block.
[00]: Min.
[01]: Middle 1
[10]: Middle 2
[11]: Max.
Set the current value of rough clamp in analog block.
[00]: Min.
[01]: Middle 1
[10]: Middle 2
[11]: Max.
Select the way to clamps the input signal at YPbPr
signal decodeing.
[0]: Y: analog sync tip clamp
Pb, Pr: analog backporch clamp
[1]: Y: analog sync tip clamp
Pb, Pr: analog middle clamp
Reserved
MS0973-E-01
65
2008/07