AK8854VQ Datasheet, PDF (43/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

(mV*)
NTSC/PAL
601 Code
714/700 235
357/350 127
180/175 ⁶³
[AK8854VQ]
100% White
50IRE threshold with
setting SLLVL = [1]
25IRE threshold with
setting SLLVL = [0]
L L _{````</sub> L L H H <sub>````} H H
`````
Cb/Y <sub>``````</sub> Cr/Y
Cb/Y <sub>``````</sub> Cr/Y
*Threshold values (mV) are approximate.
L: <sup>Value set by Low Slice</sup>
Data Set Register
H: <sup>Value set by High Slice</sup>
L
Data Set Register
```````
High/Low conversion is performed for either the Cb/Y or the Cr/Y combination. The above figure is an
example of the conversion points for Cb/Y.
It must be set VBIDEC[1:0]=[00] (Black level output ) at YPbPr or RGB input.
7.5 Output pin status
For normal operation, the output from the DATA[7:0], VD_F, DVALID_F, NSIG, and HD pins can each
be fixed at Low via the Output Control Register. Note, however, that the OE, PDN, and RSTN pin
states will have priority regardless of these register settings.
7.6 VLOCK mechanism
The AK8854 synchronizes internal operation with the input signal frame structure. If, for example, the
frame structure of the input signal comprises 524 lines, the internal operation will have a structure of 524
lines per frame. This mechanism is termed the VLOCK mechanism. If an input signal changes from a
structure of 525 lines per frame to one of 524 lines per frame, internal operation will change accordingly,
and the VLOCK mechanism will go to UnLock via a pull-in process. In such case, the UnLock status
can be confirmed via the control register [VLOCK-bit]. Note that the time required for locking of the
VLOCK mechanism upon channel or other input signal switching will be about 4 frames.
MS0973-E-01
43
2008/07